1. Field of the Invention
The present invention relates to a memory cell structure of a nonvolatile semiconductor memory.
2. Description of the Related Art
In a nonvolatile semiconductor memory provided with a memory cell of a stack gate structure having a floating gate and a control gate, such as a NAND-type flash memory, memory capacity in every generation can be increased by reducing the size of the memory cell in accordance with a scaling rule.
However, when reducing the size of the memory cell, since a parasitic capacitance between adjacent cells increases and a coupling ratio is reduced, other means for maintaining or improving the coupling ratio should be considered.
One of the means is a method in which areas of the floating gate and the control gate face with each other are made to increase by a three-dimensional cell structure to maintain a capacitance coupling ratio.
For instance, a structure in which the floating gate is made to have a vertical long shape (column shape, protrusion shape or the like) to a surface of a semiconductor substrate is a promising candidate of the memory cell structure of a next generation as the structure capable of improving the coupling ratio without enlarging a size of the memory cell (for instance, refer to patent documents, Jpn. Pat Appln. KOKAI Publication No. 2004-22819, U.S. Pat. No. 6,908,817).
A drawback of this structure exists in a point that the floating gates of the adjacent two memory cells increase simultaneously together with areas faced with each other, thus deterioration of the cell characteristics caused by threshold fluctuation is generated by an interference effect between cells.
This deterioration of the cell characteristics exerts a significant influence on the NAND-type flash memory to which a multilevel cell (MLC) technique is applied and which the MLC technique necessitates delicate threshold control.